This invention relates to a semiconductor device comprising a semiconductor body having device regions defining at least one transistor with first and second electrodes and a protection element having a device region forming a pn junction within the semiconductor body and covered by an electrode layer connected via an electrode to one of the first and second electrodes for providing a conductive path between the first and second electrodes when a voltage above a threshold voltage is applied to the first electrode.
Such a protection device is provided for protecting the transistor and other device elements against the excessive voltages which may arise when, for example, the semiconductor device is subjected to an electrostatic discharge such as may arise when the semiconductor device or one of its connector pins is accidently touched by a person. The protection element is designed to provide a good conductive path during the application of such an excessive voltage so as to prevent damage to or destruction of the semiconductor device and to return to its normal non-conducting state when the excessive voltage is removed.
The subject of ESD (ElectroStatic Discharge) protection for CMOS integrated circuits is described in, for example, a paper entitled `ESD protection reliability in 1 .mu.m CMOS technologies` by C. Duvuury et al published in the proceedings of the IEEE International Reliability Physics Symposium Volume IRPS-86 at pages 199-205.
As the packing density of integrated circuits increases and thus the size of the individual transistors is reduced, the importance of forming good low-resistance contacts increases. As discussed in the aforementioned paper, it is conventional to provide an electrode layer, usually in the form of a metal silicide layer, on a device region to be contacted to improve the electrical connection to the subsequent contact metallization. However, the provision of such electrode layers severely degrades the performance of ESD protection devices within the integrated circuits as explained in the aforementioned paper. It has been proposed, as set out in, for example, the English language Abstract for Japanese Patent Application Publication No. JP-A-63-70553 to reduce this problem by masking the area of the ESD protection devices during the formation of the metal silicide electrode layer. This, however, introduces an additional masking stage into the manufacturing process, so increasing costs.